STM32MP157D datasheet(38/259 Pages) STMICROELECTRONICS

38 / 259 page

Functional overview

STM32MP157A/D

38/259

DS12504 Rev 5

The block also includes the EXTI IOport selection.

Each interrupt or event can be set as secure in order to restrict access to secure software

only.

3.19

Cyclic redundancy check calculation unit (CRC1, CRC2)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

programmable polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps computing a signature

of the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

3.20

Flexible memory controller (FMC)

The FMC controller main features are the following:

•

Interface with static-memory mapped devices including:

–

NOR Flash memory

–

Static or pseudo-static random access memory (SRAM, PSRAM)

–

NAND Flash memory with 4-bit/8-bit BCH hardware ECC

•

8-,16-bit data bus width

•

Independent chip select control for each memory bank

•

Independent configuration for each memory bank

•

Write FIFO

3.21

Dual Quad-SPI memory interface (QUADSPI)

The QUADSPI is a specialized communication interface targeting single, dual or quad SPI

Flash memories. It can operate in any of the three following modes:

•

indirect mode: all the operations are performed using the QUADSPI registers

•

status polling mode: the external Flash memory status register is periodically read and

an interrupt can be generated in case of flag setting

•

memory-mapped mode: the external Flash memory is mapped to the address space

and is seen by the system as if it was an internal memory

Both throughput and capacity can be increased two-fold using dual-flash mode, where two

Quad-SPI Flash memories are accessed simultaneously.

QUADSPI is coupled with a delay block (DLYBQS) allowing the support of external data

frequency above 100 MHz.

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