STM32H747AI datasheet(24/252 Pages) STMICROELECTRONICS

Nome de Peças	STM32H747AI

Descrição Electrónicos	Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI

PDF	252 Pages

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Fabricante Electrônico	STMICROELECTRONICS [STMicroelectronics]

Página de início	http://www.st.com

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Functional overview

STM32H747xI/G

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DS12930 Rev 1

Error code correction (ECC)

Over the product lifetime, and/or due to external events such as radiations, invalid bits in

memories may occur. They can be detected and corrected by ECC. This is an expected

behavior that has to be managed at final-application software level in order to ensure data

integrity through ECC algorithms implementation.

SRAM data are protected by ECC:

•

7 ECC bits are added per 32-bit word.

•

8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.

The ECC mechanism is based on the SECDED algorithm. It supports single-error correction

and double-error detection.

3.3.3

ART™ accelerator

The ART™ (adaptive real-time) accelerator block speeds up instruction fetch accesses of

the Cortex®-M4 core from D1-domain internal memories (Flash memory bank 1, Flash

memory bank 2, AXI SRAM) and from D1-domain external memories attached via Quad-

SPI controller and Flexible memory controller (FMC).

The ART™ accelerator is a 256-bit cache line using 64-bit WRAP4 accesses from the 64-bit

AXI D1 domain. The acceleration is achieved by loading selected code into an embedded

cache and making it instantly available to Cortex®-M4 core, thus avoiding latency due to

memory wait states.

Figure 3. shows the block schematic and the environment of the ART accelerator.

STM32H747AI Folha de dados(PDF) 24 Page - STMicroelectronics