R7FA2L1AB2DFM datasheet(33/110 Pages) RENESAS

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2.3.1

Frequency

Table 2.15

Operation frequency in high-speed operating mode

Conditions: VCC = AVCC0 = 1.8 to 5.5 V

Parameter

Symbol

Min

Typ

Max*5

Unit

Operation

frequency

System clock (ICLK)*1*2*4

1.8 to 5.5 V

0.032768 —

MHz

Peripheral module clock (PCLKB) *4

1.8 to 5.5 V

—

Peripheral module clock (PCLKD)*3 *4

1.8 to 5.5 V

—

Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or

erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as

1.5 MHz cannot be set.

Note 2. The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy

of the clock source.

Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC12 is in use.

Note 4. See section x, Clock Generation Circuit for the relationship of frequencies between ICLK, PCLKB, and PCLKD.

Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed

operation, see Table 2.19.

Table 2.16

Operation frequency in middle-speed mode

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Min

Typ

Max*5

Unit

Operation

frequency

System clock (ICLK)*1*2*4

1.8 to 5.5 V

0.032768 —

MHz

1.6 to 1.8 V

0.032768 —

Peripheral module clock (PCLKB) *4

1.8 to 5.5 V

—

1.6 to 1.8 V

—

Peripheral module clock (PCLKD)*3 *4

1.8 to 5.5 V

—

1.6 to 1.8 V

—

Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or

erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as

1.5 MHz cannot be set.

Note 2. The frequency accuracy of ICLK must be ± 1.0% while programming or erasing the flash memory. Confirm the frequency accuracy

of the clock source.

Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC12 is in use.

Note 4. See section x, Clock Generation Circuit for the relationship of frequencies between ICLK, PCLKB, and PCLKD.

Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed

operation, see Table 2.19.

Table 2.17

Operation frequency in low-speed mode

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Min

Typ

Max*5

Unit

Operation

frequency

System clock (ICLK)*1*2*4

1.6 to 5.5 V

0.032768 —

MHz

Peripheral module clock (PCLKB) *4

1.6 to 5.5 V

—

Peripheral module clock (PCLKD)*3 *4

1.6 to 5.5 V

—

Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory.

Note 2. The frequency accuracy of ICLK must be ± 1.0% while programming or erasing the flash memory. Confirm the frequency accuracy

of the clock source.

Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC12 is in use.

Note 4. See section x, Clock Generation Circuit for the relationship of frequencies between ICLK, PCLKB, and PCLKD.

Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed

operation, see Table 2.19.

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0100 Rev.1.00

Aug 06, 2020

Page 33 of 110

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