CS4210 datasheet(18/102 Pages) NSC

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Operational Description (Continued)

When the IntEvent.cycleInconsistent condition occurs, the

IT and IR DMA controllers continue processing running

contexts normally, except that contexts with the Context-

Control.cycleMatchEnable bit set remain inactive and

cycleMatch processing is, in effect, disabled. To re-enable

cycleMatch processing, software must first stop the IT and/

or IR contexts for which cycleMatch is enabled (by clearing

ContextControl.run and waiting for ContextControl.active to

clear, then clearing the IntEvent.cycleInconsistent interrupt

(read BAR0+Offset 84h[23]). The stopped IR contexts may

then be started. The stopped IT contexts may also be

started, but software should not schedule any transmits to

occur for these contexts for at least two cycles immediately

following the clearing of the interrupt condition.

Table 3-5 is a register format for the eight Isochronous

Transmit Context Control Set/Clear registers. Refer to Sec-

tion 4.4.26.1 "Isoch Transmit Context Control Register" on

page 84 for further register information.

Table 3-5. IsochTx[7:0]ContextControl Set/Clear Register Formats

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

IsochTxnContextControl Set Register

IsochTxnContextControl Clear Register

cycleMatch

RSVD

event code

CS4210 Folha de dados(PDF) 18 Page - National Semiconductor (TI)