PWCT2106AFVMHPR datasheet(22/65 Pages) NXP

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5.7 Standard input pin capacitance

Table 13. Standard input pin capacitance

Symbol

Description

Min.

Max.

Unit

CIN_D

Input capacitance: digital pins

—

NOTE

Please refer to External System Oscillator electrical

specifications for EXTAL/XTAL pins.

5.8 Device clock specifications

Table 14. Device clock specifications 1

Symbol

Description

Min.

Max.

Unit

High Speed run mode2

fSYS

System and core clock

—

112

MHz

fBUS

Bus clock

—

MHz

fFLASH

Flash clock

—

MHz

Normal run mode (MWCT101xS series) 3

fSYS

System and core clock

—

MHz

fBUS

Bus clock

—

404

MHz

fFLASH

Flash clock

—

26.67

MHz

VLPR mode5

fSYS

System and core clock

—

MHz

fBUS

Bus clock

—

MHz

fFLASH

Flash clock

—

MHz

fERCLK

External reference clock

—

MHz

1. Refer to the section Feature comparison for the availability of modes and other specifications.

2. Only available on some devices. See section Feature comparison.

3. With SPLL as system clock source.

4. 48 MHz when fSYS is 48 MHz

5. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any

other module.

I/O parameters

MWCT101XS Data Sheet, Rev. 3, 12/2019

NXP Semiconductors

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