PWCT1036AFVLLPR datasheet(2/65 Pages) NXP

2 / 65 page

• Communications interfaces

– Up to three Low Power Universal Asynchronous Receiver/Transmitter (LPUART/LIN) modules with DMA support

and low power availability

– Up to three Low Power Serial Peripheral Interface (LPSPI) modules with DMA support and low power availability

– Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support and low power availability

– Up to three FlexCAN modules (with optional CAN-FD support)

– FlexIO module for emulation of communication protocols and peripherals (UART, I2C, SPI, I2S, LIN, PWM, etc).

• Safety and Security

– Cryptographic Services Engine (CSEc) implements a comprehensive set of cryptographic functions as described in the

SHE (Secure Hardware Extension) Functional Specification. Note: CSEc (Security) or EEPROM writes/erase will

trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The

device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.

– 128-bit Unique Identification (ID) number

– Error-Correcting Code (ECC) on flash and SRAM memories

– System Memory Protection Unit (System MPU)

– Cyclic Redundancy Check (CRC) module

– Internal watchdog (WDOG)

– External Watchdog monitor (EWM) module

• Timing and control

– Up eight independent 16-bit FlexTimers (FTM) module, offering up to 64 standard channels (IC/OC/PWM)

– One 16-bit Low Power Timer (LPTMR) with flexible wake up control

– Two Programmable Delay Blocks (PDB) with flexible trigger system

– One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels

– 32-bit Real Time Counter (RTC)

• I/O and package

– 64-pin LQFP, 100-pin LQFP, 100-pin MAPBGA package options

• 16 channel DMA with up to 63 request sources using DMAMUX

MWCT101XS Data Sheet, Rev. 3, 12/2019

NXP Semiconductors

PWCT1036AFVLLPR Folha de dados(PDF) 2 Page - NXP Semiconductors