PWCT2116AFVLLPR datasheet(4/65 Pages) NXP

4 / 65 page

1 Block diagram

The figure below shows a superset high level architecture block diagram of the device.

Other devices within the family have a subset of the features. See Feature comparison for

chip specific values.

Mux

Trace

port

Crossbar switch (AXBS-Lite)

eDMA

DMA

MUX

Core

Peripheral bus controller

CRC

WDOG

DSP

NVIC

ITM

FPB

DWT

AWIC

SWJ-DP

TPIU

JTAG &

Serial Wire

Arm Cortex M4F

AHB-AP

PPB

GPIO

Mux

FPU

Clock

SPLL

LPO

128 kHz

Async

512B

TCD

LPIT

LPI2C

FlexIO

Flash memory

controller

Code flash

Data flash

Low Power

Timer

12-bit ADC

TRGMUX

LPUART

LPSPI

FlexCAN

FlexTimer

PDB

generation

LPIT

Peripherals present

on all MWCT101xS devices

Peripherals present

on selected MWCT101xS devices

Key:

Device architectural IP

on all MWCT101xS devices

FIRC

48 MHz

SOSC

8-40 MHz

(see the "Feature Comparison"

memory

4-40 MHz

QuadSPI

RTC

CMP

8-bit DAC

SIRC

8 MHz

FlexRAM/

SRAM

1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from

accessing restricted memory regions. This system MPU provides memory protection at the

level of the Crossbar Switch. Each Crossbar master (Core, DMA) can be assigned

different access rights to each protected memory region. The Arm M4 core version in this family

does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory

accesses. In this document, the term MPU refers to NXP’s system MPU.

2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"

chapter of the MWCT101xS Series Reference Manual.

section in the RM)

ERM

EWM

MCM

Lower region

Upper region

Main SRAM2

Code Cache

EIM

LMEM

controller

LMEM

QSPI

CSEc3

System MPU1

3: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this

use case is not allowed to execute simultaneously. The device needs to switch to RUN mode (80 MHz) to

execute CSEc (Security) or EEPROM writes/erase.

Figure 1. High-level architecture diagram for the MWCT101xS family

Block diagram

MWCT101XS Data Sheet, Rev. 3, 12/2019

NXP Semiconductors

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