MWCT2024AFVLLPR datasheet(13/65 Pages) NXP

13 / 65 page

4.5 LVR, LVD and POR operating requirements

Table 5. VDD supply LVR, LVD and POR operating requirements

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

VPOR

Rising and falling VDD POR detect voltage

1.1

1.6

2.0

VLVR

LVR falling threshold (RUN, HSRUN, and

STOP modes)

2.50

2.58

2.7

VLVR_HYST

LVR hysteresis

—

VLVR_LP

LVR falling threshold (VLPS/VLPR modes)

1.97

2.22

2.44

VLVD

Falling low-voltage detect threshold

2.8

2.875

VLVD_HYST

LVD hysteresis

—

VLVW

Falling low-voltage warning threshold

4.19

4.305

4.5

VLVW_HYST

LVW hysteresis

—

VBG

Bandgap voltage reference

0.97

1.00

1.03

1. Rising threshold is the sum of falling threshold and hysteresis voltage.

4.6 Power mode transition operating behaviors

All specifications in the following table assume this clock configuration:

• RUN Mode:

• Clock source: FIRC

• SYS_CLK/CORE_CLK = 48 MHz

• BUS_CLK = 48 MHz

• FLASH_CLK = 24 MHz

• HSRUN Mode:

• Clock source: SPLL

• SYS_CLK/CORE_CLK = 112 MHz

• BUS_CLK = 56 MHz

• FLASH_CLK = 28 MHz

• VLPR Mode:

• Clock source: SIRC

• SYS_CLK/CORE_CLK = 4 MHz

• BUS_CLK = 4 MHz

• FLASH_CLK = 1 MHz

• STOP1/STOP2 Mode:

• Clock source: FIRC

• SYS_CLK/CORE_CLK = 48 MHz

General

MWCT101XS Data Sheet, Rev. 3, 12/2019

NXP Semiconductors

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