TPS25750D datasheet(5/74 Pages) TI

5 / 74 page

Table 6-1. TPS25750D Pin Functions

TYPE(1)

RESET DESCRIPTION

NAME

NO.

ADCIN1

Hi-Z

Configuration Input. Connect to a resistor divider to LDO_3V3.

ADCIN2

Hi-Z

Configuration Input. Connect to a resistor divider to LDO_3V3.

CC1

I/O

Hi-Z

I/O for USB Type-C. Filter noise with recommended capacitor to GND

(CCCy).

CC2

I/O

Hi-Z

I/O for USB Type-C. Filter noise with recommended capacitor to GND

(CCCy).

GND

11, 12, 14, 31

—

Ground. Connect to ground plane.

GPIO0

GPIO

Hi-Z

General purpose digital I/O. Tie to ground when unused.

GPIO1

GPIO

Hi-Z

General purpose digital I/O. Tie to ground when unused.

GPIO2

Hi-Z

General purpose digital I/O. Tie to ground when unused.

GPIO3

Hi-Z

General purpose digital I/O. Tie to ground when unused.

GPIO4(USB_P)

I/O

Hi-Z

General purpose digital I/O. Tie to ground when unused.This may be

connected to D+ for BC1.2 support.

GPIO5(USB_N)

I/O

Hi-Z

General purpose digital I/O. Tie to ground when unused. This may be

connected to D- for BC1.2 support.

GPIO6

Hi-Z

General purpose digital I/O. Tie to ground when unused.

GPIO7

Hi-Z

General purpose digital I/O. Tie to ground when unused.

I2Cs_SCL

Hi-Z

I2C slave serial clock input. Tie to pullup voltage through a resistor. May be

grounded if unused.

I2Cs_SDA

I/O

Hi-Z

I2C slave serial data. Open-drain input/output. Tie to pullup voltage through a

resistor. May be grounded if unused.

I2Cs_IRQ

Hi-Z

I2C slave interrupt. Active low. Connect to external voltage through a pull-up

resistor. This can be re-configured to GPIO10. Tie to ground if unused.

I2Cm_SCL

Hi-Z

I2C master serial clock. Open-drain output. Tie to pullup voltage through a

resistor. Can be grounded if unused.

GPIO11

Hi-Z

General purpose digital I/O. Tie to ground when unused.

I2Cm_SDA

I/O

Hi-Z

I2C master serial data. Open-drain input/output. Tie to pullup voltage through

a resistor. Can be grounded if unused.

I2Cm_IRQ

Hi-Z

I2C master interrupt. Active low. Connect to external voltage through a pull-up

resistor.Tie to ground when unused. This can be re-configured to GPIO12.

LDO_1V5

—

Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This

pin cannot source current to external circuits.

LDO_3V3

—

Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with

capacitance CLDO_3V3 to GND.

DRAIN

15, 30

N/A

—

Connects to drain of internal FET.

PP5V

34, 35

—

5-V System Supply to VBUS, supply for CCy pins as VCONN.

PPHV

20, 21, 22

I/O

High-voltage sinking node in the system.

VBUS_IN

23, 24, 25

I/O

5-V to 20-V input.

VBUS

32, 33

5-V output from PP5V input to LDO. Bypass with capacitance CVBUS to GND.

VIN_3V3

—

Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.

(1)

I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output

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TPS25750

SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020

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