TPS25750_V01 datasheet(34/74 Pages) TI

34 / 74 page

9.3.3.1.7 PP_CABLE Local Overtemperature Shut Down (OTSD)

When PP_CABLE clamps the current, the temperature of the switch will begin to increase. When the local

temperature sensors of PP_5V or PP_CABLE detect that TJ>TSD_PP5V, the PP_CABLE switch is disabled and

latched off within tPP_CABLE_off. The port then enters the USB Type-C ErrorRecovery state.

9.3.3.1.8 PP_CABLE UVLO

If the PP5V pin voltage falls below its undervoltage lock out threshold (VPP5V_UVLO), then the PP_CABLE switch

is automatically disabled within tPP_CABLE_off.

9.3.3.2 TPS25750D Internal Sink Path

The TPS25750D has internal controls for internal FETs (GATE_VSYS and GATE_VBUS as shown in Figure

9-13) that require that VBUS_IN be above VVBUS_UVLO before being able to enable the sink path. Figure 9-13

shows a diagram of the sink path. When a sink path is enabled, the circuitry includes a slew rate control loop to

ensure that external switches do not turn on too quickly (SS). The TPS25750D senses the PPHV and VBUS

voltages to control the gate voltages to enable or disable the FETs.

The sink-path control includes overvoltage protection (OVP) and reverse current protection (RCP).

PP_HV

Gate Control and Sense

PPHV

VBUS

Figure 9-13. Internal Sink Path

9.3.3.2.1 Overvoltage Protection (OVP)

The application firmware enables the OVP and configures it based on the expected VBUS voltage. If the voltage

on VBUS surpasses the configured threshold VOVP4VSYS = VOVP4RCP/rOVP, then GATE_VSYS is

automatically disabled within tPPHV_FSD to protect the system. If the voltage on VBUS surpasses the

configured threshold VOVP4RCP, then GATE_VBUS is automatically disabled within tPPHV_OVP. When

VVBUS falls below VOVP4RCP - VOVP4RCPH, GATE_VBUS is automatically re-enabled within tPPHV_ON

since the OVP condition has cleared. This allows two sinking power paths to be enabled simultaneously and

GATE_VBUS will be disabled when necessary to ensure that VVBUS remains below VOVP4RCP.

While the TPS25750D is in BOOT mode in a dead-battery scenario (that is VIN_3V3 is low), it handles an OVP

condition slightly differently. As long as the OVP condition is present, GATE_VBUS and GATE_VSYS are

disabled. Once the OVP condition clears, both GATE_VBUS and GATE_VSYS are re-enabled. Since this is a

dead-battery condition, the TPS25750D will be drawing approximately IVIN_3V3, ActSnk from VBUS during this

time to help discharge it.

TPS25750

SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020

www.ti.com

Submit Document Feedback

Product Folder Links: TPS25750

TPS25750 Folha de dados(PDF) 34 Page - Texas Instruments