Data Sheet

ADP1074

Rev. D | Page 13 of 32

Pin No.

Mnemonic

Description

16

COMP

Compensation Node on the Secondary Side. This pin is the output of the transconductance (gm) amplifier. This

pin is referenced to AGND2.

17

FB

Feedback Node on the Secondary Side. Set up the resistive divider from the output voltage such that the

nominal voltage, when the power supply is in regulation, is 1.2 V. Reference this pin to AGND2.

18

OVP

Output Overvoltage Protection (OVP). The OVP threshold is set at 1.36 V. Connect a resistive divider from OVP to

the output and AGND2.

19

VDD2

Input Supply on the Secondary Side. Connect VDD2 to the output voltage of the power supply for a self driven

configuration. Connect a 4.7 μF capacitor from VDD2 to AGND2. The size of this capacitor can be reduced if the

input voltage to VDD2 is guaranteed stable.

20

VREG2

5 V Regulated Low Dropout (LDO) Output for Internal Bias and Powering of the Drivers of the Synchronous

Rectifiers. Do not use VREG2 as a reference or load. Connect a 1 μF capacitor from VREG2 to AGND2.

21

AGND2

Analog Ground on the Secondary Side. Star connect AGND2 to PGND2. Use AGND2 for differential sensing of the

output voltage between the FB pin and AGND2.

22

PGND2

Power Ground on the Secondary Side. Star connect PGND2 to AGND2.

23

SR2

MOSFET Driver Output 2 for the Synchronous Rectifier MOSFET. This PWM controls the freewheeling switch.

24

SR1

MOSFET Driver Output 1 for the Synchronous Rectifier MOSFET. This PWM is in phase with NGATE.