IS25LP016D-RBLE:P datasheet(92/114 Pages) ISSI

Nome de Peças	IS25LP016D-RBLE:P

Descrição Electrónicos	SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

PDF	114 Pages

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Fabricante Electrônico	ISSI [Integrated Silicon Solution, Inc]

Página de início	http://www.issi.com

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IS25LP016D

IS25WP016D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B10

03/09/2020

AUTOBOOT REGISTER WRITE OPERATION (WRABR, 15h)

Before the WRABR command can be accepted, a Write Enable (WREN) command must be issued and decoded

by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The WRABR command is entered by shifting the instruction and the data bytes, least significant byte first, most

significant bit of each byte first. The WRABR data is 32 bits in length.

CE# must be driven high after the 32nd bit of data has been latched. If not, the WRABR command is not executed.

As soon as CE# is driven high, the WRABR operation is initiated. While the WRABR operation is in progress, Status

“1” during the WRABR

operation, and is a 0 when it is completed. When the WRABR cycle is completed, the WEL is set to

“0”.

Figure 8.78 WRABR Sequence In SPI mode

Instruction = 15h

CE #

SCK

Data In 1

Mode 3

Mode 0

High Impedance

...

Figure 8.79 WRABR Sequence In QPI Mode

15h

Mode 3

Mode 0

7:4

3:0

CE#

SCK

IO[3:0]

Data In 1

...

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