W5100 datasheet(39/72 Pages) WIZNET

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5. Functional Descriptions

By setting some register and memory operation, W5100 provides internet connectivity. This

chapter describes how it can be operated.

5.1 Initialization

◼

Basic Setting

For the W5100 operation, select and utilize appropriate registers shown below.

1. Mode Register (MR)

2. Interrupt Mask Register (IMR)

3. Retry Time-value Register (RTR)

4. Retry Count Register (RCR)

For more information of above registers, refer to the “Register Descriptions”.

◼

Setting network information

Below register is for basic network configuration information to be configured according to

the network environment.

1. Gateway Address Register (GAR)

2. Source Hardware Address Register (SHAR)

3. Subnet Mask Register (SUBR)

4. Source IP Address Register (SIPR)

The Source Hardware Address Register (SHAR) is the H/W address to be used in MAC layer, and

can be used with the address that manufacturer has been assigned. The MAC address can be

assigned from IEEE. For more detail, refer to IEEE homepage.

◼

Set socket memory information

This stage sets the socket tx/rx memory information. The base address and mask address of

each socket are fixed and saved in this stage.

In case of, assign 2K rx memory per socket.

{

RMSR = 0x55; // assign 2K rx memory per socket.

gS0_RX_BASE = chip_base_address + RX_memory_base_address(0x6000);

gS0_RX_MASK = 2K – 1 ; // 0x07FF, for getting offset address within assigned socket 0 RX

memory.

gS1_RX_BASE = gS0_BASE + (gS0_MASK + 1);

gS1_RX_MASK = 2K – 1 ;

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