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H5GQ2H24AFR-R0C Folha de dados(PDF) 99 Page - Hynix Semiconductor

Nome de Peças H5GQ2H24AFR-R0C
Descrição Electrónicos  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
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Fabricante Electrônico  HYNIX [Hynix Semiconductor]
Página de início  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C Folha de dados(HTML) 99 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
99
H5GQ2H24AFR
Figure 64. Preamble Timing Diagram
DBI
DO
DO
DBI
n+7
n+7
n
n
DO
DO
n+7
n
CL = CLmrs = 6
Bank a,
Col n
Col n
CK
CK#
DQ6
DBI#
T0
T1
T4
T5
T5n
T6n
T6
T7n
T8
T9
T10
T7
WCK#
DONʹT CARE
TRANSITIONING DATA
DQ7
WCK
ODT Disabled
ODT Enabled
ODT Enabled
ODT
2.  WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
4.  DQ6, DQ7 and the DBI# pin are shown to illustrate the DQ preamble pattern. RDBI is Enabled (MR1 A8=0).
5.  Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
1.  CLmrs = 6 is shown as an example.  Actual supported values will be found in the MR and AC timings sections.
3.  EDC may be on or off.  See Figure 58 for EDC Timing.
Notes:
6.  tWCK2DQO = 0 is shown for illustration purposes.
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
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COMMAND
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