9240LP datasheet(2/18 Pages) MAXWELL

2 / 18 page

01.10.05 REV 6

All data sheets are subject to change without notice

14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC

9240LP

TABLE 1. 9240LP PIN DESCRIPTION

PIN NUMBER

NAME

DESCRIPTION

DVSS

Digital Ground

2, 29

AVSS

Analog Ground

DVDD

5V Digital Supply

4, 28

AVDD

5V Analog Supply

No Connect

DRVDD

Digital Output Driver Supply

CLK

Clock Input Pin

LPTSTATUS

A 0 to 5V square-wave is output during the deci-

sion time and protect time. Normally low.

LPTBIT

The LPT circuit will crowbar the power supplies

to the 9240 for as long as a logic high is applied.

Used to verify operation of the LPT. Normally a

logical low or ground is applied to this input.

No Connect

BIT 14

Least Significant Data Bit (LSB)

12-23

BIT 13-BIT 2

Data Output Bits

BIT 1

Most Significant Data Bits (MSB)

OTR

Out of Range

26, 27, 30

No Connect

SENSE

Reference Select

VREF

Reference I/O

REFCOM

Reference Common

34, 38

No Connect

BIAS 1

1. See Speed/Power programmability section.

Power/Speed Programming

CAPB

Noise Reduction Pin

CAPT

Noise Reduction Pin

CML

Common-Mod Level (Midsupply)

LPTVREF

Protected Reference I/O

VINA

Analog Input Pin (+)

VINB

Analog Input Pin (-)

LPTDVDD

Protected 5V Digital Supply

LPTAVDD

Protected 5V Analog Supply

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