Application Information

TS472

16/20

4.7

Standby mode

When the standby command is set, the time required to set the output stages (differential

outputs and 2.0V bias output) in high impedance and the internal circuitry in shutdown mode is

4.8

Layout considerations

The TS472 has sensitive pins to connect C1, C2 and Rgs. To obtain high power supply

rejection and low noise performance, it is mandatory that the layout track to these component is

as short as possible.

Decoupling capacitors on Vcc and bypass pin are needed to eliminate power supply drops. In

addition, the capacitor location for the dedicated pin should be as close to the device as

possible.

4.9

Demoboard

A demoboard for the TS472 is available.

For more information about this demoboard, please refer to Application Note AN

can be found on www.st.com.

Figure 37. Top layer

Figure 38. Bottom layer

Figure 39. Component location