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CDP1824CD3 Folha de dados(PDF) 3 Page - Intersil Corporation

Nome de Peças CDP1824CD3
Descrição Electrónicos  High-Reliability CMOS 32-Word x 8-Bit Static Random-Access Memory
PDF  5 Pages
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Fabricante Electrônico  INTERSIL [Intersil Corporation]
Página de início  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP1824CD3 Folha de dados(HTML) 3 Page - Intersil Corporation

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44
Read Cycle Dynamic Electrical Specifications
Input tR, tF ≤ 15ns, CL = 50pF
PARAMETER
SYMBOL
TEST
CONDITIONS
LIMITS
UNITS
-55oC, +25oC+125oC
VDD
(V)
MIN
MAX
MIN
MAX
Access Time From Address Change
tAA
5
-
610
-
825
ns
10
-
320
-
375
ns
Access Time From Chip Select
tDOA
5
-
610
-
825
ns
10
-
320
-
375
ns
Output Active From MRD
tAM
5
-
610
-
825
ns
10
-
320
-
375
ns
NOTE:
1. Minimum timing for valid data output longer times will initiate an earlier, but invalid output.
FIGURE 1. READ CYCLE TIMING DIAGRAM
tAM
(NOTE 1)
tAA
tDOA
(NOTE 1)
HIGH IMPEDANCE
MRD
MA
CS
DATA OUT
CDP1824/3, CDP1824C/3



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