RA4W1 datasheet(48/105 Pages) RENESAS

48 / 105 page

R01DS0359EJ0100 Rev.1.00

Page 48 of 105

Mar 31, 2020

RA4W1 Datasheet

2. Electrical Characteristics

2.3.3

Reset Timing

Note 1.

When OFS1.LVDAS = 0.

Note 2.

When OFS1.LVDAS = 1.

Figure 2.30

Reset input timing at power-on

Figure 2.31

Reset input timing (1)

Table 2.24

Reset timing

Parameter

Symbol

Min

Typ

Max

Unit

Test

conditions

RES pulse width

At power-on

tRESWP

Figure 2.30

Other than above

tRESW

μs

Figure 2.31

Wait time after RES cancellation

(at power-on)

LVD0: enable*1

tRESWT

0.7

-ms

Figure 2.30

LVD0: disable*2

0.3

Wait time after RES cancellation

(during powered-on state)

LVD0: enable*1

tRESWT2

0.5

-ms

Figure 2.31

LVD0: disable*2

0.05

Internal reset cancellation time (Watchdog

timer reset, SRAM parity error reset,

SRAM ECC error reset, Bus master MPU

error reset, Bus slave MPU error reset,

Stack pointer error reset, Software reset)

LVD0: enable*1

tRESWT3

0.6

-ms

LVD0: disable*2

0.15

VCC

RES

tRESWP

Internal reset

tRESWT

RES

Internal reset

tRESWT2

tRESW

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