AM652X datasheet(254/277 Pages) TI1

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MCU_OSPI[x]_CLK

OSPI/QSPI/SPI

device clock input

OSPI/QSPI/SPI

device IOy, CS#

MCU_OSPI[x]_D[y],

MCU_OSPI[x]_CSn[z]

OSPI_Board_01

254

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

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Applications, Implementation, and Layout

7.2

Peripheral- and Interface-Specific Design Information

7.2.1

DDR Board Design and Layout Guidelines

The goal of the AM65x/DRA80xM DDR Board Design and Layout Guidelines is to make the DDR3L,

DDR4, and LPDDR4 system implementation straightforward for all designers. Requirements have been

distilled down to a set of layout and routing rules that allow designers to successfully implement a robust

design for the topologies that TI supports. TI only supports board designs using DDR3L, DDR4, and

LPDDR4 memories that follow the guidelines in this document.

7.2.2

OSPI Board Design and Layout Guidelines

The following section details the routing guidelines that must be observed when routing the OSPI

interfaces.

7.2.2.1

No Loopback & Internal Pad Loopback

•

The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device

•

The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450pS

(~7cm as stripline or ~8cm as microstrip)

•

50 Ω PCB routing is recommended along with series terminations, as shown in Figure 7-1

•

Propagation delays and matching:

–

A to B < 450ps

–

Matching skew: < 60pS

*0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed

Figure 7-1. OSPI Interface High Level Schematic

7.2.2.2

External Board Loopback

•

The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device

•

The MCU_OSPI[x]_LBCLKO output signal must be looped back into the MCU_OSPI[x]_DQS input

•

The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to

should

approximately

equal

half

the

signal

propagation

delay

from

the

MCU_OPSI[x]_LBCLKO pin to the MCU_OSPI[x]_DQS pin ((C to D)/2). See the note below.

•

The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to

B) must be approximately equal to the signal propagation delay of the control and data signals

between the flash device and the SoC device (E to F, or F to E)

•

50 Ω PCB routing is recommended along with series terminations, as shown in Figure 7-2

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