AM652X datasheet(246/277 Pages) TI1

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246

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

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Detailed Description

6.4.5

Peripherals

6.4.5.1

ADC

The Analog-to-Digital Converter (ADC) module contains a single 12-bit ADC which can be multiplexed to

any 1 of 8 analog inputs (channels).

For more information, see Analog-to-Digital Converter (ADC) section in the device TRM.

6.4.5.2

CAL

The Camera Adapter Layer Subsystem (CALSS) is based on a Camera Adaptation Layer (CAL) module,

which enables connection to multiple camera sensors through shared MIPI D-PHY module and LVDS

receiver.

CAL Module (CALSS0) is a very flexible subsystem that enables connection to multiple cameras

supporting MIPI CSI-2 over D-PHY serial interface, a LVDS serial interface, and a traditional parallel

interface. It also includes an internal write DMA engine connected to VBUSM interface.

For more information, see Camera Adapter Layer (CAL) Subsystem section in the device TRM.

6.4.5.3

CPSW2G

The two-port Gigabit Ethernet MAC (MCU_CPSW0) subsystem provides Ethernet packet communication

for the device and is configured in a similar manner as a two-port Ethernet switch. MCU_CPSW0 features

the Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII),

and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management.

For more information, see Gigabit Ethernet MAC (MCU_CPSW0) section in the device TRM.

6.4.5.4

DCC

The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time

execution of an application. Specifically, the DCC is designed to detect drifts from the expected clock

frequency. The desired accuracy can be programed based on calculation for each application. The DCC

measures the frequency of a selectable clock source using another input clock as a reference.

For more information, see Dual Clock Comparator (DCC) section in the device TRM.

6.4.5.5

DDRSS

The DDR subsystem in this device comprises DDR controller, DDR PHY and wrapper logic to integrate

these blocks in the device. The DDR subsystem is referred to as DDRSS0 and is used to provide an

interface to external SDRAM devices which can be utilized for storing program or data. DDRSS0 is

accessed via MSMC, and not directly through the system interconnect.

For more information, see DDR Subsystem (DDRSS) section in the device TRM.

6.4.5.6

DSS

The Display Subsystem (DSS) is a flexible, multi-pipeline subsystem that supports high-resolution display

outputs. DSS includes input pipelines providing multi-layer blending with transparency to enable on-the-fly

composition. Various pixel processing capabilities are supported, such as color space conversion and

scaling, among others. DSS includes a DMA engine, which allows direct access to the frame buffer

(device system memory). Display outputs can connect seamlessly to an Open LVDS Display Interface

transmitter (OLDITX), or can directly drive device pads as a parallel video output interface.

For more information, see Display Subsystem (DSS) section in the device TRM.

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