STM32MP153F datasheet(14/254 Pages) STMICROELECTRONICS

14 / 254 page

Description

STM32MP153C/F

14/254

DS12503 Rev 3

Description

The STM32MP153C/F devices are based on the high-performance dual-core Arm®

Cortex®-A7 32-bit RISC core operating at up to 800 MHz. The Cortex-A7 processor

includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each

CPU and a 256-Kbyte level2 cache. The Cortex-A7 processor is a very energy-efficient

application processor designed to provide rich performance in high-end wearables, and

other low-power embedded and consumer applications. It provides up to 20% more single

thread performance than the Cortex-A5 and provides similar performance than the Cortex-

A9.

The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and Cortex-

A17 processors, including virtualization support in hardware, NEON™, and 128-bit AMBA®4

AXI bus interface.

The STM32MP153C/F devices also embed a Cortex® -M4 32-bit RISC core operating at up

to 209 MHz frequency. Cortex-M4 core features a floating point unit (FPU) single precision

which supports Arm® single-precision data-processing instructions and data types. The

Cortex® -M4 supports a full set of DSP instructions and a memory protection unit (MPU)

which enhances application security.

The STM32MP153C/F devices provide an external SDRAM interface supporting external

memories up to 8-Gbit density (1 Gbyte), 16 or 32-bit LPDDR2/LPDDR3 or DDR3/DDR3L

up to 533 MHz.

The STM32MP153C/F devices incorporate high-speed embedded memories with

708 Kbytes of Internal SRAM (including 256 Kbytes of AXI SYSRAM, 3 banks of 128 Kbytes

each of AHB SRAM, 64 Kbytes of AHB SRAM in backup domain and 4 Kbytes of SRAM in

backup domain), as well as an extensive range of enhanced I/Os and peripherals connected

to APB buses, AHB buses, a 32-bit multi-AHB bus matrix and a 64-bit multi layer AXI

interconnect supporting internal and external memories access.

STM32MP153F Folha de dados(PDF) 14 Page - STMicroelectronics