STM32MP153D datasheet(30/254 Pages) STMICROELECTRONICS

30 / 254 page

Functional overview

STM32MP153A/D

30/254

DS12502 Rev 3

3.9

Reset and clock controller (RCC)

The clock and reset controller manages the generation of all the clocks, as well as the clock

gating and the control of the system and peripheral resets. It provides a high flexibility in the

choice of clock sources and allows application of clock ratios to improve the power

consumption. In addition, on some communication peripherals that are capable to work with

two different clock domains (either a bus interface clock or a kernel peripheral clock), the

system frequency can be changed without modifying the baudrate.

3.9.1

Clock management

The devices embed four internal oscillators, two oscillators with external crystal or

resonator, three internal oscillators with fast startup time and four PLLs.

The RCC receives the following clock source inputs:

•

Internal oscillators:

–

64 MHz HSI clock (1% accuracy)

–

4 MHz CSI clock

–

32 kHz LSI clock

•

External oscillators:

–

8-48 MHz HSE clock

–

32.768 kHz LSE clock

The RCC provides four PLLs:

•

The PLL1 is dedicated to the MPU clocking

•

The PLL2 provides:

–

The clocks for the AXI-SS (including APB4, APB5, AHB5 and AHB6 bridges)

–

The clocks for the DDR interface

•

The PLL3 provides:

–

The clocks for the MCU, and its bus matrix (including the APB1, APB2, APB3,

AHB1, AHB2, AHB3 and AHB4)

–

The kernel clocks for peripherals

•

The PLL4 is dedicated to the generation of the kernel clocks for various peripherals

The system starts on the HSI clock. The user application can then select the clock

configuration.

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