STM32L4P5CE datasheet(29/310 Pages) STMICROELECTRONICS

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DS12903 Rev1

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STM32L4P5xx

Functional overview

Stop 1

LPR

Off

LSE

LSI

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DACx (x=1,2)

OPAMPx (x=1,2)

USARTx (x=1...5)(6)

LPUART1(6)

I2Cx (x=1...4)(7)

LPTIMx (x=1,2)

***

All other peripherals are

frozen

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

USARTx

(x=1...5)(6)

LPUART1(6)

I2Cx (x=1...4)(7)

LPTIMx (x=1,2)

OTG_FS(8)

Stop 2

LPR

Off

LSE

LSI

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

I2C3(7)

LPUART1(6)

LPTIMx (x=1,2)

***

All other peripherals are

frozen

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

I2C3(7)

LPUART1(6)

LPTIMx (x=1,2)

Standby

LPR

Powered

Off

SRAM2

LSE

LSI

BOR, RTC, IWDG

***

All other peripherals are

powered off

***

I/O configuration can be

floating, pull-up or pull-

down

Reset pin

5 I/Os (WKUPx)(9)

BOR, RTC, IWDG

OFF

Powered

Off

Shutdown

OFF

Powered

Off

Powered

Off

LSE

RTC

***

All other peripherals are

powered off

***

I/O configuration can be

floating, pull-up or pull-

down(10)

Reset pin

5 I/Os (WKUPx)(9)

RTC

1. LPR means Main regulator is OFF and Low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

4. The SRAM1, SRAM2 and SRAM3 clocks can be gated on or off independently.

5. SMPS mode can be used in Stop 0 mode, but no significant power gain can be expected.

6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or

received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. OTG_FS wakeup by resume from suspend and attach detection protocol event.

Table 4. STM32L4P5xx modes overview (continued)

Mode

Regulator(1)

CPU

Flash

SRAM

Clocks

DMA and peripherals(2)

Wakeup source

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