CS5321 datasheet(14/36 Pages) CIRRUS

14 / 36 page

CS5321/22

DS454F2

CS5322 SWITCHING CHARACTERISTICS (continued)

Notes: 24. If MCLK is removed, the modulator will enter the power down mode.

25. Excludes MCLK input. MCLK should be driven with a signal having rise and fall times of 25 ns or faster.

26. Only the rising edge of MSYNC relative to MCLK is used to synchronize the device. MSYNC can return

low at any time as long as it remains high for at least one MCLK cycle.

Parameter

Symbol

Min

Typ

Max

Units

MCLK Frequency

(Note 24)

0.512

1.024

1.1

MHz

MCLK Duty Cycle

Rise Times:

Any Digital Input

(Note 25)

Any Digital Output

trise

100

200

Fall Times:

Any Digital Input

(Note 25)

Any Digital Output

tfall

100

200

SYNC Setup Time to CLKIN rising

tss

SYNC Hold Time after CLKIN rising

tsh

CLKIN edge to MCLK edge

tmss

-30-

MCLK rising to Valid MDATA

tmsh

-50-

MSYNC Delay from MCLK rising

(Note 26)

tmsd

-90-

t mss

CL K IN

SY N C

LS Y N C *

MC L K

MS Y N C

MD A T A

MF L G

* Inte rnal tim in g s ign a l gen era te d in th e C S 5 32 2

FIL T E R

SA M P L E S

DA T A

t msd

t msh

VA LID D A T A

VA L ID D A T A

t sh

t ss

Figure 17. CS5321/CS5322 Interface Timing

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