EM78P451SWM datasheet(13/54 Pages) EMC

13 / 54 page

EM78P451S

8-Bit Microcontroller with OTP ROM

Product Specification (V1.0) 06.01.2004

• 9

(This specification is subject to change without further notice)

4.1.11 RD (SPIC: SPI Control Register)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0D

SPIC/RD

CES

SPIE

SRO

SSE

SBRS2

SBRS1

SBRS0

Bit 7 (CES): Clock Edge Select bit

0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on

hold during the low level.

1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on

hold during the high level.

Bit 6 (SPIE): SPI Enable bit

0= Disable SPI mode

1= Enable SPI mode

Bit 5 (SRO): SPI Read Overflow bit

0 = No overflow

1 = A new data is received while the previous data is still being held in the

SPIB register. In this situation, the data in SPIS register will be destroyed.

To avoid setting this bit, users had better read SPIRB register even if only

the transmission is implemented.

NOTE

This can only occur in slave mode.

Bit 4 (SSE): SPI Shift Enable bit

0 = Reset as soon as the shifting is complete, and the next byte is ready

to shift.

1 = Start to shift, and keep on 1 while the current byte is still being

transmitted.

NOTE

This bit will reset to 0 at every one-byte transmission by the hardware

Bit 2~Bit 0 (SBRS): SPI Baud Rate Select bits

SPI baud rate table is illustrated in SPI section in later pages.

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