56F802 datasheet(13/40 Pages) FREESCALE

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JTAG/OnCE

56F802 Technical Data, Rev. 7

Freescale Semiconductor

2.8 JTAG/OnCE

Table 2-10 JTAG/On-Chip Emulation (OnCE) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

TCK

Input

(Schmitt)

Input, pulled

low internally

Test Clock Input—This input pin provides a gated clock to synchronize the

test logic and shift serial data to the JTAG/OnCE port. The pin is connected

internally to a pull-down resistor.

TMS

Input

(Schmitt)

Input, pulled

high internally

Test Mode Select Input—This input pin is used to sequence the JTAG TAP

controller’s state machine. It is sampled on the rising edge of TCK and has an

on-chip pull-up resistor.

TDI

Input

(Schmitt)

Input, pulled

high internally

Test Data Input—This input pin provides a serial input data stream to the

JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip

pull-up resistor.

TDO

Output

Tri-stated

Test Data Output—This tri-statable output pin provides a serial output data

stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR

controller states, and changes on the falling edge of TCK.

TRST

Input

(Schmitt)

Input, pulled

high internally

Test Reset—As an input, a low signal on this pin provides a reset signal to the

JTAG TAP controller. To ensure complete hardware reset, TRST should be

asserted at power-up and whenever RESET is asserted. The only exception

occurs in a debugging environment, since the OnCE/JTAG module is under

the control of the debugger. In this case it is not necessary to assert TRST

when asserting RESET. Outside of a debugging environment RESET should

be permanently asserted by grounding the signal, thus disabling the

OnCE/JTAG module on the device.

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