THCX222R05 datasheet(3/11 Pages) CEL

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THCX222R05_Rev.1.00_E

THine Electronics, Inc.

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Pin Description

Pin Name

Pin No

Type

Description

RX1P

Super-Speed CML Signal Input of Channel1(CH1)

RX1N

Super-Speed CML Signal Input of CH1

TX1P

Super-Speed CML Signal Output of CH1

TX1N

Super-Speed CML Signal Output of CH1

RX2P

Super-Speed CML Signal Input of Channel2(CH2)

RX2N

Super-Speed CML Signal Input of CH2

TX2P

Super-Speed CML Signal Output of CH2

TX2N

Super-Speed CML Signal Output of CH2

Channel Enable

0 : Power Down

1 : Normal Operation

EQAC1U

4LI

CH1 Rx Equalizer Peak Gain & High Linear Mode setting

This pin along with EQAC1L allows for up to 16 settings.

EQAC1L

4LI

CH1 Rx Equalizer Peak Gain & High Linear Mode setting

This pin along with EQAC1U allows for up to 16 settings.

EQAC2U

4LI

CH2 Rx Equalizer Peak Gain & High Linear Mode setting

This pin along with EQAC2L allows for up to 16 settings.

EQAC2L

4LI

CH2 Rx Equalizer Peak Gain & High Linear Mode setting

This pin along with EQAC2U allows for up to 16 settings.

EQDC1

4LI

CH1 Equalizer DC Gain Setting

EQDC2

4LI

CH2 Equalizer DC Gain Setting

MODESEL

4LI

Chip Operation Mode Select, if EN=1

0 : CH1/2 enable, RxDetect/SignalDetect enable

R : CH1/2 enable, RxDetect enable, SignalDetect disable

F : CH1/2 enable, RxDetect/SignalDetect disable

1 : CH1 enable, CH2 disable, RxDetect/SignalDetect disable

VCC

1, 10, 16, 25

PWR

Power Supply Pin for On-chip Regulator.

GND

4,5,6,7,13,

19,20,21,

22,28,31

GND

Ground. Must be tied to the PCB ground plane through an

array of vias.

Pin#31 is exposed pad ground.

CI: CML Input Buffer, CO: CML Output Buffer

I: LVCMOS Input Buffer, 4LI: 4-Level LVCMOS Input Buffer,

PWR: Power Supply, GND: Ground

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