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ADP3168 Folha de dados(PDF) 21 Page - Analog Devices

Nome de Peças ADP3168
Descrição Electrónicos  6-Bit, Programmable 2-, 3-, 4-Phase Synchronous Buck Controller
PDF  24 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

ADP3168 Folha de dados(HTML) 21 Page - Analog Devices

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ADP3168
Rev. B | Page 21 of 24
CIN SELECTION AND INPUT CURRENT
DI/DT REDUCTION
In continuous inductor current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × VOUT/VIN and an amplitude of one-nth of the
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by
A
A
I
D
N
I
D
I
CRMS
O
CRMS
5
.
10
1
125
.
0
3
1
65
125
.
0
1
1
=
−
×
×
×
=
−
×
×
×
=
(34)
Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2,000 hours of life. This makes it advisable
to further derate the capacitor or choose a capacitor rated at a
higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
three 2,200 µF, 16 V Nichicon capacitors with a ripple current
rating of 3.5 A each.
To reduce the input current di/dt to a level below the
recommended maximum of 0.1 A/µs, an additional small
inductor (L > 1 µH @ 15 A) should be inserted between the
converter and the supply bus. That inductor also acts as a filter
between the converter and the primary power source.
()
()
FLHOT
NL
FLCOLD
NL
OLD
SC
NEW
CS
V
V
V
V
R
R
−
−
×
=
2
2
(35)
TUNING PROCEDURE FOR THE ADP3168
1.
Build circuit based on compensation values computed
from design spreadsheet.
2.
Hook up dc load to circuit, turn on, and verify operation.
Also check for jitter at no-load and full-load.
DC Loadline Setting
3.
Measure output voltage at no-load (VNL). Verify that it is
within tolerance.
4.
Measure output voltage at full-load cold (VFLCOLD). Let
board set for ~10 minutes at full-load and measure output
(VFLHOT). If there is a change of more than a couple of
millivolts, adjust RCS1 and RCS2 using Equations 35 and 37.
5.
Repeat Step 4 until cold and hot voltage measurements
remain the same.
6.
Measure output voltage from no-load to full-load using 5 A
steps. Compute the loadline slope for each change and then
average to get overall loadline slope (ROMEAS).
7.
If ROMEAS is off from RO by more than 0.05 mΩ, use the
following to adjust the RPH values:
()
()
O
OMEAS
OLD
PH
NEW
PH
R
R
R
R
×
=
(36)
8.
Repeat Steps 6 and 7 to check loadline and repeat
adjustments if necessary.
9.
Once complete with dc loadline adjustment, do not change
RPH, RCS1, RCS2, or RTH for rest of procedure.
10. Measure output ripple at no-load and full-load with scope
and make sure it is within specifications.
()
()
(
)
()
(
)
(
)
(
)
()
()
(
)
()
()
C
TH
C
TH
OLD
CS
NEW
CS
OLD
CS
C
TH
OLD
CS
C
TH
OLD
CS
NEW
CS
R
R
R
R
R
R
R
R
R
R
°
°
°
°
−
−
×
−
+
×
+
=
25
25
1
2
1
25
1
25
1
2
1
1
(37)
0
10
20
30
40
50
60
70
80
90
100
20
30
010
40
50
60
OUTPUT CURRENT (A)
Figure 14. Efficiency of the Circuit of Figure 11 vs. Output Current



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