PSD813F1 datasheet(21/110 Pages) STMICROELECTRONICS

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PSD813F1

INSTRUCTIONS

An instruction is defined as a sequence of specific

operations. Each received byte is sequentially de-

coded by the PSD and not executed as a standard

write operation. The instruction is executed when

the correct number of bytes are properly received

and the time between two consecutive bytes is

shorter than the time-out value. Some instructions

are structured to include READ operations after

the initial WRITE operations.

The sequencing of any instruction must be fol-

lowed exactly. Any invalid combination of instruc-

tion bytes or time-out between two consecutive

bytes while addressing Flash memory will reset

the device logic into READ mode (Flash memory

reads like a ROM device). An invalid combination

or time-out while addressing the EEPROM block

will cause the offending byte to be interpreted as a

single operation.

The PSD supports these instructions (see Table

8., page 20):

Flash memory:

Erase memory by chip or sector

Suspend or resume sector erase

Program a Byte

Reset to READ mode

Read Flash Identifier value

Read Sector Protection Status

EEPROM:

Write data to OTP Row

Read data from OTP Row

Power down memory

Enable Software Data Protect (SDP)

Disable SDP

Return from read OTP Row read mode or

power down mode.

These

instructions

are

detailed

Table

8., page 20. For efficient decoding of the instruc-

tions, the first two bytes of an instruction are the

coded cycles and are followed by a command byte

or confirmation byte. The coded cycles consist of

writing the data AAh to address X555h during the

first cycle and data 55h to address XAAAh during

the second cycle. Address lines A15-A12 are don’t

cares during the instruction WRITE cycles. How-

ever, the appropriate sector select signal (FSi or

EESi) must be selected.

Power-down Instruction and Power-up Mode

EEPROM Power Down Instruction. The

EE-

PROM can enter power down mode with the help

of the EEPROM power down instruction (see Ta-

ble 8., page 20). Once the EEPROM power down

instruction is decoded, the EEPROM memory can-

not be accessed unless a Return instruction (also

in Table 8., page 20) is decoded. Alternately, this

power down mode will automatically occur when

the APD circuit is triggered (see section entitled

Automatic Power-down (APD) Unit and Power-

down Mode, page 65). Therefore, this instruction

is not required if the APD circuit is used.

Power-up Mode. The PSD internal logic is reset

upon power-up to the READ mode. Any write op-

eration to the EEPROM is inhibited during the first

5ms following power-up. The FSi and EESi select

signals, along with the write strobe signal, must be

in the false state during power-up for maximum se-

curity of the data contents and to remove the pos-

sibility of a byte being written on the first edge of a

write strobe signal. Any write cycle initiation is

locked when VCC is below VLKO.

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