V62SLASH13624-01XE-R datasheet(10/77 Pages) TI1

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MSP430F2132-EP

SLAS913A – JULY 2013 – REVISED AUGUST 2013

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4.5 Special Function Registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

not allocated to a functional purpose are not physically present in the device. Simple software access is provided

with this arrangement.

Legend

Bit can be read and written.

rw-0, 1

Bit can be read and written. It is Reset or Set by PUC.

rw-(0), (1)

Bit can be read and written. It is Reset or Set by POR.

SFR bit is not present in device.

Table 4. Interrupt Enable 1

Address

00h

ACCVIE

NMIIE

OFIE

WDTIE

rw-0

WDTIE

Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval

timer mode.

OFIE

Oscillator fault interrupt enable

NMIIE

(Non)maskable interrupt enable

ACCVIE

Flash access violation interrupt enable

Table 5. Interrupt Enable 2

Address

01h

UCB0TXIE

UCB0RXIE

UCA0TXIE

UCA0RXIE

rw-0

UCA0RXIE

USCI_A0 receive-interrupt enable

UCA0TXIE

USCI_A0 transmit-interrupt enable

UCB0RXIE

USCI_B0 receive-interrupt enable

UCB0TXIE

USCI_B0 transmit-interrupt enable

Table 6. Interrupt Flag Register 1

Address

02h

NMIIFG

RSTIFG

PORIFG

OFIFG

WDTIFG

rw-0

rw-(0)

rw-(1)

rw-1

rw-(0)

WDTIFG

Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.

OFIFG

Flag set on oscillator fault

RSTIFG

External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.

PORIFG

Power-on reset interrupt flag. Set on VCC power up.

NMIIFG

Set via RST/NMI pin

Table 7. Interrupt Flag Register 2

Address

03h

UCB0TXIFG

UCB0RXIFG

UCA0TXIFG

UCA0RXIFG

rw-1

rw-0

rw-1

rw-0

UCA0RXIFG

USCI_A0 receive-interrupt flag

UCA0TXIFG

USCI_A0 transmit-interrupt flag

UCB0RXIFG

USCI_B0 receive-interrupt flag

UCB0TXIFG

USCI_B0 transmit-interrupt flag

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