ADS5553

SLWS158 − FEBRUARY 2005

www.ti.com

16

APPLICATION INFORMATION

THEORY OF OPERATION

The ADS5553 is a low-power, dual 14 bit, 65 MSPS,

CMOS, switched capacitor, pipeline ADC that operates

from a single 3.3 V supply. The conversion process is

initiated by a falling edge of the external input clock.

Once the signal is captured by the input S&H, the input

sample is sequentially converted by a series of small

resolution stages, with the outputs combined in a digital

correction logic block. Both the rising and the falling

clock edges are used to propagate the sample through

the pipeline every half clock cycle. This process results

in a data latency of 16.5 clock cycles, after which the

output data is available as a 14 bit parallel word, coded

in binary two’s complement format.

INPUT CONFIGURATION

The analog input for the ADS5553 consists of a

differential sample-and-hold architecture implemented

using a switched capacitor technique, shown in

Figure 28.

VINCM

1V

+

INM

INP

−

S2, : On Resistance : 7.5 Ω to 15 Ω

All switches Off Resistance : 10 GΩ

All switches are on in sampling phase which is approximately one half of a clock period.

Figure 28. Analog Input Stage