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M65818AFP Folha de dados(PDF) 12 Page - Renesas Technology Corp |
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M65818AFP Folha de dados(HTML) 12 Page - Renesas Technology Corp |
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12 / 39 page ![]() M65818AFP Rev.1.00, Sep.04.2003, page 12 of 38 • Input Formats of DATA, BCK, and LRCK LRCK BCK MSB 16 cycle DATA (16bit) MSB 16 cycle 1/fsi, 1/2fsi, 1/4fsi Left Right DATA (24bit) MSB MSB 24 cycle 24 cycle MSB DATA (20bit) MSB 20 cycle 20 cycle LSB LSB LSB LSB LSB LSB MSB first right justified(16bit, 20bit, 24bit) LRCK BCK DATA (24bit) Left Right MSB first left justified(24bit) MSB MSB 24cycle LSB LSB 1/fsi, 1/2fsi, 1/4fsi 24cycle LSB LSB LRCK BCK DATA (24bit) Left Right 24 cycle 24 cycle MSB MSB LSB first right justified(24bit) 1/fsi, 1/2fsi, 1/4fsi LRCK BCK DATA (24bit) MSB MSB 24 cycle 24 cycle 1/fsi, 1/2fsi, 1/4fsi Left Right I 2S(24bit) 1 BCK LSB LSB 1 BCK 5.4. EXBCK, EXWCK, EXDATAL, EXDATAR, EXIOSEL 62 63 60 61 59 When "input signal mode" is "external 8fs data mode", regardless of a setup of EXIOSEL pin, the data of 8fs rate are inputted from EXDATAL, EXDATAR pins. By setup of serial control "System1 mode:bit21", Primary Side Synchronous Input or Secondary Side Synchronous Input can be selected. In case an external 8fs data input is secondary side synchronous , the data is inputted to Gain Control Block. |
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