Everest Semiconductor

Confidential

ES8396

Revision 5.0

7

March 2018

instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you

must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the

register. There are no acknowledge bit after data to be written or read, this is the only

Chip Address

R/W

Register Address

Data to be written

001000

AD0

0

ACK

RAM

ACK

DATA

Chip Address

R/W

Register Address

001000

AD0

0

ACK

RAM

Chip Address

R/W

Data to be read

001000

AD0

1

ACK

Data

6. DIGITAL AUDIO INTERFACE

The device provides many formats of serial audio data interface to the input of the DAC or

output from the ADC through LRCK, BCLK (SCLK) and DACDAT/ADCDAT pins. These formats are

device on the rising edge of SCLK. ADC data is out at ADCDAT on the falling edge of SCLK. The

relationship of SDATA (DACDAT/ADCDAT), SCLK and LRCK with these formats are shown through

Figure 2 to Figure 6.

n-2 n-1

n

3

2

1

1 SCLK

MSB

LSB

LEFT CHANNEL

n-2 n-1

n

3

2

1

1 SCLK

MSB

LSB

RIGHT CHANNEL

SDATA

SCLK

LRCK

n-2 n-1

n

3

2

1

MSB

LSB

LEFT CHANNEL

n-2 n-1

n

3

2

1

MSB

LSB

RIGHT CHANNEL

SDATA

SCLK

LRCK

Figure 3 Left Justified Serial Audio Data Format Up To 24-bit