PIFE32251B-R47MS datasheet(32/96 Pages) TI1

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TPS65094

SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019

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Detailed Description

(1)

All Power Good signals must immediately deassert at the loss of any of the qualifying signals, or at the occurrence of a fault condition.

6.3

Feature Description

6.3.1

Power Good (PGOOD)

The TPS65094x device provides information on status of VRs through two Power Good signals or pins.

Table 6-2 defines which signals are required to assert the PGOOD signals.

Table 6-2. Power Good Summary

POWER GOOD(1)

QUALIFYING SIGNALS (LOGICAL AND)

RSMRSTB

✓

PCH_PWROK

✓

6.3.2

All registers are reset if any of the following conditions are met:

•

VSYS pin voltage drops below 5.4 V

•

Falling edge of PMICEN for OTPs where LDOA1 is not "Always On"

•

Falling edge of THERMTRIPB while RSMRSTB = 1

•

Power fault of any regulator where xx_FLTMSK = 0 (see Section 6.6.27, PWR_FAULT_MASK1

•

PMIC critical temperature shutdown

•

Software shutdown (writing 1 to the SDWN bit in the FORCESHUTDN register, see Figure 6-35)

Additionally, BUCK1 and BUCK2 VID registers are reset on the falling edge of SLP_S0IXB and SLP_S3B.

6.3.3

SMPS Voltage Regulators

The buck controllers integrate gate drivers for external power stages with programmable current limit (set

by an external resistor at ILIMx pin), which allows for optimal selection of external passive components

based on the desired system load. The buck converters include integrated power stage and require a

minimum number of pins for power input, inductor, and output voltage feedback input. Combined with

high-frequency switching, all these features allow use of inductors in small form factor, thus reducing the

total cost and size of the system.

BUCK3–BUCK6 have selectable auto- and forced-PWM mode through the BUCKx_MODE bit in the

BUCKxCTRL register. In default auto mode, the VR automatically switches between PWM and PFM

depending on the output load to maximize efficiency. The host cannot select Forced PWM mode for other

SMPS VRs as they stay in auto mode at all times.

See Table 6-3 and Table 6-4 for the full voltage tables for all SMPS regulators.

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