CY2220
Document #: 38-07206 Rev. *A
Page 2 of 11
Pin Summary
Name
Pins
Description
VSSREF
1
3.3V Reference ground
VDDREF
4
3.3V Reference voltage supply
VSSPCI
7, 13, 19
3.3V PCI ground
VDDPCI
10, 16, 22
3.3V PCI voltage supply
VSS3V66
32, 33
3.3V AGP and Hub Link ground
VDD3V66
29, 36
3.3V AGP and Hub Link voltage supply
VSSUSB
24
3.3V USB ground
VDDUSB
27
3.3V USB voltage supply
VSSCPU
40, 46
3.3V CPU ground
VDDCPU
43, 49
3.3V CPU voltage supply
VSSMEM
53
3.3V Memory ground
VDDMEM
56
3.3V Memory voltage supply
AVSS
37
Analog ground for PLL and Core
AVDD
38
Analog voltage supply to PLL and Core
IREF
39
Reference current for external biasing
XTALIN[1]
5
Reference crystal input
XTALOUT[1]
6
Reference crystal feedback
CPUCLK [0–3]
42, 45, 48, 51
CPU clock outputs
CPUCLK [0–3]B
41, 44, 47, 50
Inverse CPU clock outputs
PCICLK [0–9]
8, 9, 11, 12, 14, 15, 17,
18, 20, 21
PCI clock outputs, synchronously running at 33.33 MHz
MemRef
55
MemRef clock output, drives memory clock generator
MemRefB
54
MemRefB clock output 180 degrees out of phase with MemRef
3V66_ [0–3]
30, 31, 34, 35
AGP and Hub Link clock outputs, running at 66 MHz
USBCLK [0–1]/Sel[A–B]
25, 26
Sel [A–B] inputs are sensed then internally latched on power-up be-
fore the pins are used for 48-MHz USB clock outputs
REFCLK[0–1]/MultSel[0–1]
2, 3
MultSel[0–1] inputs are sensed then internally latched on power-up
before the pins are Reference clock outputs, 14.318 MHz
PWR_DWN
28
Active LOW input, powers down part when asserted
SPREAD[2]
52
Active LOW input, enables spread spectrum when asserted
SEL133
23
CPU frequency select input (See Function Table)
Notes:
1.
For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. For crystals with different CLOAD, please refer to the application note, “Crystal Oscillator
Topics.”
2.
Input is static HIGH or LOW. Frequency of toggling cannot exceed 30 MHz.
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