AD9957SLASHPCBZ datasheet(31/61 Pages) AD

31 / 61 page

Data Sheet

AD9957

Rev. F | Page 31 of 61

The circled numbers in Figure 44 indicate specific events,

explained as follows:

Event 1—an I/O update or profile change activates the RAM

bidirectional ramp mode.

Event 2—the RT pin switches to Logic 1. The state machine

initializes to the start address of RAM Segment Register 0 and

begins incrementing the RAM address counter.

Event 3—the RT pin remained at Logic 1 long enough for the

state machine to reach the end address of RAM Segment

Event 4—the RT pin switches to Logic 0. The state machine

initializes to the end address of RAM Segment Register 1, resets

the internal timer, and begins decrementing the RAM address

counter.

Event 5—the RT pin switches to Logic 1. The state machine

initializes to the start address of RAM Segment Register 0,

resets the internal timer, and begins incrementing the RAM

address counter.

Event 6—the RT pin switches to Logic 0. The state machine

initializes to the end address of RAM Segment Register 1, resets

the internal timer, and begins decrementing the RAM address

counter.

Event 7—the RT pin remained at Logic 0 long enough for the

state machine to reach the start address of RAM Segment

Event 8—the RT pin switches to Logic 1. The state machine

initializes to the start address of RAM Segment Register 0,

resets the internal timer, and begins incrementing the RAM

address counter.

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