NET2890 datasheet(45/73 Pages) ETC

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Specification

NET2890 USB Interface Controller

____________________________________________________________________________________

NetChip Technology, Inc., 1999

335 Pioneer Way, Mountain View, California 94041

TEL (650) 526-1490

FAX (650) 526-1494

http://www.netchip.com

Rev 2.0, Draft 9, July 16, 1999

5.4.4 (Address 13h; EPIRQENB) Endpoint Interrupt Enable Register (one per

Endpoint)

Bits

Description

Read

Write

Default

Value

7:6

Reserved.

Yes

Data Packet Received Interrupt Enable. When set, this bit enables a local interrupt

to be set when a data packet has been received from the host.

Yes

Data Packet Transmitted Interrupt Enable. When set, this bit enables a local

interrupt to be set when a data packet has been transmitted to the host.

Yes

Data OUT Token Interrupt Enable. When set, this bit enables a local interrupt to

be set when a Data OUT token has been received from the host.

Yes

Data IN Token Interrupt Enable. When set, this bit enables a local interrupt to be

set when a Data IN token has been received from the host.

Yes

FIFO Almost Full Interrupt Enable. When set, this bit enables a local interrupt to

be set when the number of bytes in the FIFO becomes equal to or greater than the

FIFO Almost Full Threshold.

Yes

FIFO Almost Empty Interrupt Enable. When set, this bit enables a local interrupt

to be set when the number of bytes in the FIFO becomes equal to or less than the

FIFO Almost Empty Threshold.

Yes

5.4.5 (Address 14h; EPIRQSTAT) Endpoint Interrupt Status Register (one per

Endpoint)

Bits

Description

Read

Write

Default

Value

7:6

Reserved.

Yes

Data Packet Received Interrupt. This bit is set when a data packet is received from

the host by this endpoint. This status bit is cleared by writing a 1. If this bit is set,

the Receive Handshake Mode bit is set, and another OUT token is received, a NAK

is returned to the host.

Yes

Yes/CLR

Data Packet Transmitted Interrupt. This bit is set when a data packet is

transmitted from the endpoint to the host. This status bit is cleared by writing a 1.

Yes

Yes/CLR

Data OUT Token Interrupt. This bit is set when a Data OUT token has been

received from the host. This status bit is cleared by writing a 1.

Yes

Yes/CLR

Data IN Token Interrupt. This bit is set when a Data IN token has been received

from the host. This status bit is cleared by writing a 1.

Yes

Yes/CLR

FIFO Almost Full Interrupt. This bit is set when the number of bytes in the FIFO

changes from a value less than the FIFO Almost Full Threshold to a value equal to or

greater than the threshold.

Yes

Yes/CLR

FIFO Almost Empty Interrupt. This bit is set when the number of bytes in the

FIFO changes from a value greater than the FIFO Almost Empty Threshold to a

value equal to or less than the threshold.

Yes

Yes/CLR

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