UCC28521, UCC28528

SLUS608B − JANUARY 2005 REVISED JUNE 2005

18

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APPLICATION INFORMATION

The left side of the inequality should be at least a factor of 10 lower than the middle term; the right side of the

inequality should be at least five times larger than the middle term. For the purposes of 50 Hz to 60 Hz power

factor correction, good results can be achieved with the crossover frequency set to about 10 kHz. A lower

crossover might be necessary if the switching frequency of the PWM stage is below 100 kHz, or if the

compensator gain at the crossover frequency is large (over ~40 dB).

Upon selecting the crossover frequency, select R13 to set the gain at the crossover frequency, then select C6

to place a zero at the crossover frequency and select C7 to provide a pole at half of the switching frequency.

The equations are in Table 3.

Table 2.

REFERENCE

DESIGNATOR

EQUATION

NOTES

R13

R12

2

p

f

CO(pfc)

L1

V

CT_BUFF(p−p)

V

C1

V

CT_BUFF(p−p) +

4V

C6

1

R13

2

p

f

CO(pfc)

C7

1

p

f

S(pfc)

PFC voltage loop

The voltage loop must crossover at a lower frequency than twice the ac line frequency so that voltage

directly results in third harmonic distortion on the ac line, similar to ripple on the VFF voltage.

PWM stage control

The control elements of the PWM stage are the same as a typical isolated current program mode converter.

The secondary elements include C12 to C14, D6, R22 to R25, U2 and U3, which perform the error amplifier,

compensation and isolation functions. On the primary side, VERR is connected to the node between the

opto-isolator output, U2, and a pull-up resistor, R17. Resistor R17 represents the gain in the conversion from

the output current of opto-isolator U2 and the VERR input.

Slope compensation is programmed using resistors R18 and R11, which form a summing node at ISENSE2.

The voltage at CT_BUFF is a saw-tooth waveform that swings between 1 V and 5 V.

Many applications require a duty ratio limit for the PWM stage in order to prevent transformer saturation.

Program the maximum duty ratio using the following ratio of resistors R16 to R19.

R16

R19

+

V

VREF

1

) 4

D

PWM(max)

* 1

Soft-start

The soft-start capacitor, C5, which is connected to SS2, controls the soft-start ramp of the PWM stage. The

soft-start ramp begins when the VSENSE voltage exceeds 6.75 V. In order to avoid loop saturation, the soft-start

ramp rate must be less than or equal to the open loop response of the PWM stage converter.

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