AD9528BCPZ datasheet(44/67 Pages) AD

Nome de Peças	AD9528BCPZ

Descrição Electrónicos	JESD204B Clock Generator with 14 LVDS/HSTL Outputs

PDF	67 Pages

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Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

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44 / 67 page

AD9528

Data Sheet

Rev. D | Page 44 of 67

R_DIV = 0X00

READ:

R_DIV =

WRITE:

0x207 = 0x02

WRITE:

0x207 = R_DIV × 2

WRITE:

0x0F = 0x01

READ:

PTH_EN =

WRITE:

0x202[5] = 1

WRITE:

0x207 = R_DIV

WRITE:

0x202[5] = PTH_EN

WRITE:

0x0F = 0x01

START TIMEOUT CLOCK:

TIME = 0

0x509[0] = 0

TIMEOUT CLOCK:

TIME > 100ms

YES

RAISE FLAG FOR

DEBUGGING

WRITE:

END

YES

NOTES

1. THIS ROUTINE ASSUMES THAT THE CALIBRATION DIVIDER VALUE IS SET TO A VALUE THAT IS EQUAL TO

TWICE THE PRODUCT OF THE M1 AND N2 DIVIDE VALUES. THIS IS DONE AUTOMATICALLY BY THE AD9528

EVALUATION SOFTWARE WHEN THE PRODUCT OF M1 × N2 = 15.

CREATE LOCAL

VARIABLES TO

RESTORE NORMAL

OPERATING STATE

AFTER CALIBRATION

HALVE PLL2

PFD RATE

USE LOCAL VARIABLES

TO RESTORE PLL2

NORMAL OPERATING

PFD RATE

PLL2 CALIBRATION

COMPLETE POLLING

LOOP

ISSUE VCO

CALIBRATION

COMMAND

START

M1 × N2

[15]

Figure 54. Subprocess, Issue VCO Calibration (M1 × N2 = 15)

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