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TDA9550 Folha de dados(PDF) 98 Page - NXP Semiconductors

Nome de Peças TDA9550
Descrição Electrónicos  TV signal processor-Teletext decoder with embedded m-Controller
PDF  125 Pages
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Fabricante Electrônico  PHILIPS [NXP Semiconductors]
Página de início  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TDA9550 Folha de dados(HTML) 98 Page - NXP Semiconductors

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2000 Jun 22
98
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded
µ-Controller
TDA955X/6X/8X PS/N1 series
Notes
1. When the 3.3 V supply is present and the
µ-Controller is active a ‘low-power start-up’ mode can be activated. When
all sub-address bytes have been sent and the POR and XPR flags have been cleared the horizontal output can be
switched-on via the STB-bit (subaddress 24H). In this condition the horizontal drive signal has the nominal TOFF and
the TON grows gradually from zero to the nominal value. As soon as the 8 V supply is present the switch-on procedure
(e.g. closing of the second loop) is continued.
2. On set AGC.
3. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
4. Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level as
FPLL input signal level).
5. The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a
digital control circuit which uses the clock frequency of the
µ-Controller as a reference. The required IF frequency for
the various standards is set via the IFA-IFC bits in subaddress 27H. When the system is locked the resulting IF
frequency is very accurate with a deviation from the nominal value of less than 25 kHz.
6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
7. Measured at 10 mV (RMS) top sync input signal.
8. Via this pin both the demodulated IF signal and the selected CVBS (or Y+C) signal can be supplied to the output.
The selection between both signals is realised by means of the SVO bit in subaddress 22H.
9. So called projected zero point, i.e. with switched demodulator.
BEAM CURRENT LIMITING
C.7.1
contrast reduction starting
voltage
2.8
V
C.7.2
voltage difference for full contrast
reduction
1.8
V
C.7.3
brightness reduction starting
voltage
1.7
V
C.7.4
voltage difference for full
brightness reduction
0.9
V
C.7.5
internal bias voltage
3.3
V
C.7.6
maximum allowable current
tbf
mA
FIXED BEAM CURRENT SWITCH-OFF; NOTE 62
C.8.1
discharge current during
switch-off
0.85
1.0
1.15
mA
C.8.2
discharge time of picture tube
38
ms
PEAK WHITE LIMITER AND SOFT CLIPPING; NOTES 63 AND 64
C.9.1
CVBS/Y-input signal amplitude
at which peak white limiter is
activated (black-to-white value)
PWL range (15 steps); at
max. contrast
0.55
0.85
V
C.9.2
soft clipper gain reduction
maximum contrast; note 64,
see Fig.47
8
dB
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT



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