WM8591 datasheet(40/50 Pages) WOLFSON

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WM8591

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PP Rev 1.0 May 2005

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

ADCBCP

ADC BITCLK Polarity:

0: Normal – ADCLRC sampled on rising edge of

ADCBCLK; DOUT changes on falling edge of ADCBCLK

1: Inverted - ADCLRC sampled on falling edge of

ADCBCLK; DOUT changes on rising edge of ADCBCLK

5:4

ADCWL[1:0]

ADC Input Word Length:

00: 16-bit mode

01: 20-bit mode

10: 24-bit mode

11: 32-bit mode (not supported in right justified mode)

ADCMCLKINV

ADCMCLK Polarity:

0: non-inverted

1: inverted

DACSYNCEN

Enable the DAC Synchronizer:

0: Disabled

1: Enabled

ADCHPD

ADC High Pass Filter Powerdown:

0: HP Filter Enabled

1: HP Filter Disabled

2:0

ADCRATE[2:0]

010

Master Mode ADCMCLK:ADCLRC Ratio Select:

010: 256fs

011: 384fs

100: 512fs

101: 768fs

ADCOSR

ADC Oversample Rate Select:

0: 128x oversampling

1: 64x oversampling

6:4

DACRATE[2:0]

010

Master Mode DACMCLK:DACLRC Ratio Select:

000: 128fs

001: 192fs

010: 256fs

011: 384fs

100: 512fs

101: 768fs

DACMS

DAC Master/Slave Interface Mode Select:

0: Slave Mode – DACLRC and DACBCLK are inputs

1: Master Mode –DACLRC and DACBCLK are outputs

R12 (0Ch)

0001100

Master Mode

Control

ADCMS

ADC Master/Slave Interface Mode Select:

0: Slave Mode – ADCLRC and ADCBCLK are inputs

1: Master Mode – ADCLRC and ADCBCLK are outputs

PDWN

Chip Powerdown Control (works in tandem with ADCPD and

DACPD):

0: All circuits running, outputs are active

1: All circuits in power save mode, outputs muted

ADCPD

ADC Powerdown:

0: ADC enabled

1: ADC disabled

R13 (0Dh)

0001101

PWR Down

Control

DACPD

DAC Powerdown:

0: DAC enabled

1: DAC disabled

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