4–1

4 Parameter Measurement Information

th(SDIN)

tsu(SDIN)

SCLK

SDIN

Figure 4–1. Right Justified, IIS, Left Justified Serial Protocol Timing

tsu(LRCLK)

SCLK

LRCLK

NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns)

Figure 4–2. Right, Left, and IIS Serial Mode Timing Requirement

t(MSD)

t(MLRD)

SCLK

LRCLK

(Output)

MCLK

(Output)

Figure 4–3. Serial Audio Ports Master Mode Timing

th(SDIN)

tsu(SDIN)

SCLK

LRCLK

SDIN

tsu(LRCLK)

tw(FSHIGH)

th(LRCLK)

Figure 4–4. DSP Serial Port Timing