LTC1748 datasheet(11/20 Pages) LINER

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LTC1748

1748fa

APPLICATIO S I FOR ATIO

Spurious Free Dynamic Range (SFDR)

Spurious free dynamic range is the peak harmonic or

spurious noise that is the largest spectral component

excluding the input signal and DC. This value is expressed

in decibels relative to the RMS value of a full scale input

signal.

Input Bandwidth

The input bandwidth is that input frequency at which the

amplitude of the reconstructed fundamental is reduced by

3dB for a full scale input signal.

Aperture Delay Time

The time from when a rising ENC equals the ENC voltage

to the instant that the input signal is held by the sample and

hold circuit.

Aperture Delay Jitter

The variation in the aperture delay time from conversion to

conversion. This random variation will result in noise

when sampling an AC input. The signal to noise ratio due

to the jitter alone will be:

SNRJITTER = –20log (2π) • FIN • TJITTER

CONVERTER OPERATION

The LTC1748 is a CMOS pipelined multistep converter.

The converter has four pipelined ADC stages; a sampled

analog input will result in a digitized value five cycles later,

see the Timing Diagram section. The analog input is

differential for improved common mode noise immunity

and to maximize the input range. Additionally, the differen-

tial input drive will reduce even order harmonics of the

sample-and-hold circuit. The encode input is also

differential for improved common mode noise immunity.

The LTC1748 has two phases of operation, determined by

the state of the differential ENC/ENC input pins. For brev-

ity, the text will refer to ENC greater than ENC as ENC high

and ENC less than ENC as ENC low.

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC and an interstage residue amplifier.

DIFF

REF

AMP

REF

BUF

4.7

µF

0.1

µF

0.1

µF

INTERNAL CLOCK SIGNALS

REFL

REFH

DIFFERENTIAL

INPUT

LOW JITTER

CLOCK

DRIVER

RANGE

SELECT

2.35V

REFERENCE

FIRST PIPELINED

ADC STAGE

(5 BITS)

FOURTH PIPELINED

ADC STAGE

(4 BITS)

SECOND PIPELINED

ADC STAGE

(4 BITS)

ENC

REFHA

REFLB

REFLA REFHB

ENC

SHIFT REGISTER

AND CORRECTION

MSBINV

OGND

OVDD 0.5V TO

D13

CLKOUT

1748 F01

INPUT

S/H

SENSE

VCM

AIN

–

AIN

4.7

µF

THIRD PIPELINED

ADC STAGE

(4 BITS)

OUTPUT

DRIVERS

CONTROL LOGIC

AND

CALIBRATION LOGIC

Figure 1. Functional Block Diagram

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