5

ATSAM9753

1774D–DRMSD–11/02

Notes:

1. Like all high-speed HCMOS ICs proper decoupling is mandatory for reliable operation and RFI reduction. The recommended

decoupling is 100 nF at each corner of the IC with an additional 10 µF bulk capacitor close to the X1, X2 pins.

2. The LCD display interface signals are controlled by firmware, therefore, their timing relationship is determined by firmware

only.

3. The ATSAM9753 connects to a variety of stereo DACs or Codecs from 16 to 20 bits, with Japanese or I

includes AD1857JRS, AK4352, AK4393, AK4528, PCM1718, PCM1739, PCM3001, TDA1543, TDA1545 . When Japanese

format is used, only 16 bits is supported without external circuitry.

PDWN

84

IN

Power down, active low. When power down is active, all output pins are

floating except GPIO1. The crystal oscillator is stopped. To exit from power-

down mode, PDWN should be high and RESET applied.

X1

X2

98, 99

–

11.2896 MHz (nominal) crystal connection. An external clock can also be

used at X1.

TEST[3:0]

79 - 82

IN

Test pins, should be grounded

LFT

100

–

PLL external RC network

Table 1. Pin Description by Function (Continued)

Pin Name

Pin Number

Type

Function