PIC16F62X-04SLASHP datasheet(9/170 Pages) MICROCHIP

9 / 170 page

 2003 Microchip Technology Inc.

Preliminary

DS40300C-page 7

PIC16F62X

2.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC16F62X family can be

attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC16F62X uses a Harvard architecture, in

which, program and data are accessed from separate

memories using separate buses. This improves

bandwidth over traditional Von Neumann architecture

where program and data are fetched from the same

memory. Separating program and data memory further

allows instructions to be sized differently than 8-bit

wide data word. Instruction opcodes are 14-bits wide

making it possible to have all single-word instructions.

A 14-bit wide program memory access bus fetches a

14-bit instruction in a single cycle. A two-stage pipeline

overlaps

fetch

and

execution

instructions.

Consequently, all instructions (35) execute in a single

cycle

(200 ns

20 MHz)

except

for

program

branches.

The Table below lists program memory (FLASH, Data

and EEPROM).

TABLE 2-1:

DEVICE DESCRIPTION

The PIC16F62X can directly or indirectly address its

registers, including the program counter, are mapped in

the data memory. The PIC16F62X have an orthogonal

(symmetrical) instruction set that makes it possible to

carry out any operation, on any register, using any

Addressing mode. This symmetrical nature, and lack of

‘special optimal situations’ make programming with the

PIC16F62X simple yet efficient. In addition, the learning

curve is reduced significantly.

The PIC16F62X devices contain an 8-bit ALU and

working register. The ALU is a general purpose

arithmetic unit. It performs arithmetic and Boolean

functions between data in the working register and any

The ALU is 8-bit wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically

one

operand

the

working

(W register). The other operand is a file register or an

immediate constant. In single operand instructions, the

operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register. The C and DC bits

operate as a Borrow and Digit Borrow out bit,

respectively, bit in subtraction. See the SUBLW and

SUBWF

instructions for examples.

A simplified block diagram is shown in Figure 2-1, and

a description of the device pins in Table 2-1.

Two types of data memory are provided on the

PIC16F62X

devices.

Non-volatile

EEPROM

data

memory is provided for long term storage of data such

as calibration values, lookup table data, and any other

data which may require periodic updating in the field.

This data is not lost when power is removed. The other

data memory provided is regular RAM data memory.

Regular RAM data memory is provided for temporary

storage of data during normal operation. It is lost when

power is removed.

Device

Memory

FLASH

Program

RAM

Data

EEPROM

Data

PIC16F627

1024 x 14

224 x 8

128 x 8

PIC16F628

2048 x 14

224 x 8

128 x 8

PIC16LF627

1024 x 14

224 x 8

128 x 8

PIC16LF628

2048 x 14

224 x 8

128 x 8

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