CY2283PVC-2 datasheet(7/12 Pages) CYPRESS

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CY2283

PRELIMINARY

Switching Characteristics for CY2283-2

Parameter

Output

Description

Test Conditions

Min.

Typ.

Max.

Unit

All

Output Duty Cycle

t1 = t1A ÷ t1B

TBD

CPUCLK

CPU Clock Rising and

Falling Edge Rate

Between 0.4V and 2.0V, VDDCPU = 2.5V

Between 0.4V and 2.4V, VDDCPU = 3.3V

TBD

V/ns

SDRAM,

AGP, REF0

SDRAM, AGP, REF0 Clock

Rising and Falling Edge

Rate

Between 0.4V and 2.4V

TBD

V/ns

PCI

PCI Rising and Falling

Edge Rate

Between 0.4V and 2.4V

TBD

V/ns

CPUCLK

CPU Clock Rise Time

Between 0.4V and 2.0V, VDDCPU = 2.5V

Between 0.4V and 2.4V, VDDCPU = 3.3V

TBD

CPUCLK

CPU Clock Fall Time

Between 2.0V and 0.4V, VDDCPU = 2.5V

Between 2.4V and 0.4V, VDDCPU = 3.3V

TBD

CPUCLK

CPU-CPU Clock Skew

Measured at 1.25V, VDDCPU = 2.5V

Measured at 1.5V, VDDCPU = 3.3V

TBD

CPUCLK,

PCICLK

CPU-PCI Clock Skew

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks

TBD

CPUCLK,

SDRAM

CPU-SDRAM Clock Skew

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks

TBD

PCICLK,

PCICLK

PCI-PCI Clock Skew

Measured at 1.5V

TBD

PCICLK,

AGP

PCI-AGP Clock Skew

Measured at 1.5V

TBD

t10

CPUCLK,

SDRAM

Cycle-Cycle Clock Jitter

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks

TBD

t10

PCICLK

Cycle-Cycle Clock Jitter

Measured at 1.5V

TBD

t10

AGP

Cycle-Cycle Clock Jitter

Measured at 1.5V

TBD

t11

CPUCLK,

PCICLK,

AGP,SDRAM

Power-up Time

CPU, PCI, AGP, and SDRAM clock sta-

bilization from power-up

TBD

Timing Requirement for the I

2C Bus

Parameter

Description

Min.

Max.

Unit

t12

SCLK Clock Frequency

100

kHz

t13

Time the bus must be free before a new transmission can start

4.7

µs

t14

Hold time start condition. After this period the first clock pulse is generated.

µs

t15

The LOW period of the clock

4.7

µs

t16

The HIGH period of the clock

µs

t17

Set-up time for start condition. (Only relevant for a repeated start condition.)

4.7

µs

t18

Hold time DATA

for CBUS compatible masters

for I2C devices

µs

t19

DATA input set-up time

250

t20

Rise time of both SDATA and SCLK inputs

µs

t21

Fall time of both SDATA and SCLK inputs

300

t22

Set-up time for stop condition

4.0

µs

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