AM3351 datasheet(87/252 Pages) TI1

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

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SPRS717J – OCTOBER 2011 – REVISED APRIL 2016

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Specifications

Table 5-11 summarizes the power consumption of the AM335x low-power modes.

Table 5-11. AM335x Low-Power Modes Power Consumption Summary

POWER

MODES

APPLICATION STATE

POWER DOMAINS, CLOCKS, AND

VOLTAGE SUPPLY STATES

NOM

MAX

UNIT

Standby

DDR memory is in self-refresh and

contents are preserved. Wake up

from any GPIO. Cortex-A8

context/register contents are lost

and must be saved before entering

standby. On exit, context must be

restored from DDR. For wakeup,

boot ROM executes and branches

to system resume.

Power supplies:

•

All power supplies are ON.

•

VDD_MPU = 0.95 V (nom)

•

VDD_CORE = 0.95 V (nom)

Clocks:

•

Main Oscillator (OSC0) = ON

•

All DPLLs are in bypass.

Power domains:

•

PD_PER = ON

•

PD_MPU = OFF

•

PD_GFX = OFF

•

PD_WKUP = ON

DDR is in self-refresh.

16.5

22.0

Deepsleep1

On-chip peripheral registers are

preserved. Cortex-A8

context/registers are lost, so the

application must save them to the

L3 OCMC RAM or DDR before

entering DeepSleep. DDR is in self-

refresh. For wakeup, boot ROM

executes and branches to system

resume.

Power supplies:

•

All power supplies are ON.

•

VDD_MPU = 0.95 V (nom)

•

VDD_CORE = 0.95 V (nom)

Clocks:

•

Main Oscillator (OSC0) = OFF

•

All DPLLs are in bypass.

Power domains:

•

PD_PER = ON

•

PD_MPU = OFF

•

PD_GFX = OFF

•

PD_WKUP = ON

DDR is in self-refresh.

6.0

10.0

Deepsleep0

PD_PER peripheral and Cortex-

A8/MPU register information will be

lost. On-chip peripheral register

(context) information of PD-PER

domain must be saved by

application to SDRAM before

entering this mode. DDR is in self-

refresh. For wakeup, boot ROM

executes and branches to

peripheral context restore followed

by system resume.

Power supplies:

•

All power supplies are ON.

•

VDD_MPU = 0.95 V (nom)

•

VDD_CORE = 0.95 V (nom)

Clocks:

•

Main Oscillator (OSC0) = OFF

•

All DPLLs are in bypass.

Power domains:

•

PD_PER = OFF

•

PD_MPU = OFF

•

PD_GFX = OFF

•

PD_WKUP = ON

DDR is in self-refresh.

3.0

4.3

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