LTC4449 datasheet(13/108 Pages) LINER

13 / 108 page

LTC3882-1

Rev A

For more information www.analog.com

PIN FUNCTIONS

COMP0/COMP1 (Pin 1/Pin 28): Error Amplifier Outputs.

PWM duty cycle increases with this control voltage. These

are true low impedance outputs and cannot be directly

connectedtogetherwhenactive.ForPolyPhaseoperation,

wiringFBtoVDD33willthree-statetheerroramplifieroutput

of that channel, making it a slave. PolyPhase control is

then implemented in part by connecting all slave COMP

pins together to one master error amplifier output.

TSNS0/TSNS1 (Pin 2/Pin 3): External Temperature Sense

Inputs. The LTC3882-1 supports two methods of calcula-

tion of external temperature based on forward-biased P/N

junctions between these pins and GND.

VINSNS (Pin 4): VIN Supply Sense. Connect to the VIN

power supply to provide line feedforward compensation.

A change in VIN immediately modulates the input to the

PWM comparator and inversely changes the pulse width

to provide excellent transient line regulation and fixed

modulator voltage gain. An external lowpass filter can be

added to this pin to prevent noisy signals from affecting

the loop gain.

IAVG_GND (Pin 5): IAVG Ground Reference. The same

IAVG_GND should be shared between all channels of a

PolyPhase rail and connected to system ground at a single

point. IAVG_GND may be wired directly to GND on ICs that

do not share phases with other chips.

PGOOD/PGOOD1 (Pin 6/Pin 27): Power Good Indicator

Open-DrainOutputs.Theseoutputsaredrivenlowthrough

a 30µs filter when the respective channel output is below

its programmed UV fault limit or above its programmed

OV fault limit. If used, a pull-up resistor is required in the

application. Operating voltage range is GND to VDD33.

PWM0/PWM1 (Pin 7/Pin 26): PWM Three-State Control

Outputs. These pins provide single-wire PWM switching

control for each channel to an external gate driver, DrMOS

or power block. Operating voltage range is GND to VDD33.

SYNC (Pin 8): External Clock Synchronization Input and

Open-Drain Output. If desired, an external clock can be

applied to this pin to synchronize the internal PWM chan-

nels. If the LTC3882-1 is configured as a clock master, this

pin will also pull to ground at the selected PWM switching

frequency with a 125ns pulse width. A pull-up resistor to

3.3V is required in the application if SYNC is driven by

any LTC3882-1. Minimize the capacitance on this line to

ensure its time constant is fast enough for the application.

SCL (Pin 9): Serial Bus Clock Input. A pull-up resistor to

3.3V is required in the application.

SDA (Pin 10): Serial Bus Data Input and Output. A pull-up

resistor to 3.3V is required in the application.

ALERT (Pin 11): Open-Drain Status Output. This pin may

be connected to the system SMBALERT wire-AND inter-

rupt signal and should be left open if not used. If used, a

pull-up resistor is required in the application. Operating

voltage range is GND to VDD33.

FAULT0/FAULT1 (Pin 12/Pin 13): Programmable Digital

Inputs and Open-Drain Outputs for Fault Sharing. Used

forchannel-to-channelfaultcommunicationandpropaga-

tion. These pins should be left open if not used. If used,

a pull-up resistor to 3.3V is required in the application.

RUN0/RUN1 (Pin 14/Pin 15): Run Control Inputs and

Open-Drain Outputs. A voltage above 2V is required on

these pins to enable the respective PWM channel. The

LTC3882-1 will drive these pins low under certain reset/

restart conditions regardless of any PMBus command

settings. A pull-up resistor to 3.3V is required in the ap-

plication.

ASEL0/ASEL1 (Pin 16/Pin 17): Serial Bus Address Select

Pins.Connectoptional1%resistordividersbetweenVDD25

and GND to these pins to select the serial bus interface

address. Refer to the Applications Information section

for more detail.

VOUT0_CFG/VOUT1_CFG (Pin 18/Pin 19): Output Voltage

Configuration Pins. Connect optional 1% resistor divid-

ers between VDD25 and GND to these pins to select the

output voltage for each channel. Refer to the Applications

Information section for more detail.

FREQ_CFG(Pin20):FrequencyConfigurationPin.Connect

an optional 1% resistor divider between VDD25 and GND

to this pin to configure PWM switching frequency. Refer

to the Applications Information section for more detail.

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