THC63LVDM83D_Rev.4.30_E

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Spread Spectrum Clocking Tolerant

Figure 11. Spread Spectrum Clocking Tolerant

The graph indicates the range that the IC works normally under SS clock input operation.

The results are measured with a typical sample on condition of +25Cº and 3.3V, therefore these

values are for reference and do not guarantee the performance of a product under other

circumstance.

LVDS Data Timing Diagram

Figure 12. LVDS Data Timing Diagram

Vdiff=0V

Vdiff=0V

TCLK+/-

(Differntial)

Tx+/-

X=A,B,C,D

Previous Pixel Data

Pixel Data

Tx6 Tx5 Tx4 Tx3 Tx2 Tx1 Tx0