ST10F166 datasheet(59/62 Pages) STMICROELECTRONICS

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ST10F166

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AC Characteristics (Cont’d)

Figure 23. CLKOUT and READY

Notes:

1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

2) The leading edge of the respective command depends on RW-delay.

3) READY sampled HIGH at this sampling point generates a READY controlled waitstate,

READY sampled LOW at this sampling point terminates the currently running bus cycle.

4) READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or

WR).

5) If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to

CLKOUT (eg. because CLKOUT is not enabled), it must fulfill

t37 in order to be safely synchronized. This

is guaranteed, if READY is removed in reponse to the command (see Note 4)).

6) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate

may be inserted here.

For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without

MTTC waitstate this delay is zero.

7) The next external bus cycle may start here

CLKOUT

ALE

Sync

READY

Async

READY

waitstate

READY

MUX/Tristate 6)

Running cycle

Command

RD, WR

see 6)

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